[New]
Fast PIO Transfers
Other peripherals within the computer, such as video, resolved their
throughput problems via local bus architectures providing a potential path
for improved performance. IDE local bus solutions, leveraged from the
success of video local bus, began appearing in 1992, as a way to enhance
data throughput. These solutions mapped the IDE data port to the local bus,
bypassing the ISA bus and enabling the maximization of throughput from the
media to the drive buffer, on to the host. These solutions were still not
competitive with Fast SCSI (10MB/sec) due to the "blind" transfer nature of
the PIO transfers .
"Blind PIO" transfers indicate host control of data throughput with the
host requesting data (master) and the drive responding (slave). With blind
PIO transfers, the host is unaware or "blind" when buffered drive bandwidth
is 100% available for host transfers. Because there are cases when only a
percentage of bandwidth is available, blind PIO host requests for data from
the drive are based on the worst case bandwidth availability. This means
that even when the ISA bottleneck is bypassed by connection directly to the
local bus, inability to utilize 100% drive bandwidth prevents full
optimization of host throughput.
Enhanced IDE incorporates an operation called "Flow Control Using IORDY"
(I/O Channel Ready) which allows the drive to "throttle" the host when
necessary and enable burst transfers to take advantage of 100% of the
bandwidth. Flow Control thereby gives control of the data transfer to the
drive and eliminates the inefficiencies of blind PIO by setting the host to
maximum drive bandwidth support. This means that when 100% drive bandwidth
is available, the drive will take control and transfer data to the host.
This operation, based on approved Mode 3 PIO timings of 180ns cycle times
from the Small Form Factor Committee, supports transfer rates up to
11MB/sec competitive with FAST SCSI solutions. Flow Control is enabled on
the drive by the host issuing a Set Features command, so that both the host
and drive side support this operation. Western Digital's 540MB drives
(shipping beginning September, 1993) support flow control using IORDY and
will be implemented into machines that take advantage of this feature via
low cost ASICS whose functionality will later be incorporated into core
logic chipset solutions. DMA Transfers
Although PIO is the standard transfer method supported by the industry and
presents no incompatibility issues (see footnote), another transfer option
exists that provides incremental transfer benefits beyond PIO. Direct
Memory Access (DMA) is based on data transfer directly to memory rather
than via the CPU. DMA transfers are "throttled" and therefore have
historically offered the benefit of maximizing data throughput. The
throttling mechanism associated with DMA has historically enabled improved
data transfers relative to standard PIO. Type B DMA was defined with the
arrival of Extended Industry Standard Architecture (EISA), and is specified
at 4.0MB/sec transfer rates offering an advantage to the standard 2-3MB/sec
PIO data rates. Although this is an improvement to the standard ISA bus
timings, Type B DMA remains uncompetitive with FAST SCSI timings of
10MB/sec.
With the advent of local bus solutions, a new DMA transfer has emerged in
conjuction with PCI. Type F DMA is defined to support 8.33MB/sec and
6.67MB/sec data rates, a large improvement over Type B DMA. In conjunction
with chipsets capable of supporting 6.67MB and 8.33MB/sec data rates, the
Small Form Factor Committee has approved a new multiword DMA Mode 1 timing
specification of a 150ns cycle time. This enables DMA transfers up to
13MB/sec for future data rate improvement by allowing multiple words to be
transferred for any given request command. PCI chip sets will be shipping
with both EISA (Type B) and ISA (Type F) configurations in the calendar
CYQ4'1993 time frame.
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